High speed electronic systems often have critical timing requirements which call for a periodic clock signal having a precise timing relationship with some reference signal. The improved performance of integrated circuits (ICs) and their ever-increasing complexity presents a challenge with respect to keeping such ICs synchronized when inter-operating in ever more complex systems.
For best performance, the operation of all components in a system should be highly synchronized, i.e., the maximum skew or difference in time between the significant edges of the internal clocking signals of all the components should be minimal. Because different components may have different manufacturing parameters which when taken together with additional factors, such as ambient temperature, voltage, and processing variations, could lead to large differences in the phases of the internal clocking signals of the different components, simply feeding a system-wide reference clock to the components may not be sufficient to achieve synchronization.
One way synchronization has been achieved is with the use of a delay locked loop (DLL). Various analog as well as digital implementations of DLLs are known. FIG. 1 is a block diagram of a typical DLL. The DLL includes a phase detector 10 which detects the phase difference between an input clock signal and an output clock signal of the same frequency and generates a signal related to the phase difference. The phase difference signal is in turn used by a delay control block 20 to control a variable delay chain 30 which accordingly advances or delays the timing of the output clock signal with respect to the input clock signal until the rising edge of the output clock signal is coincident with the rising edge of the input clock signal. The phase detector 10, control block 20 and delay chain 30 thus operate in a closed loop to bring the two clock signals into phase and thus synchronize the components whose operations are timed in accordance with the respective clock signals.
The range of frequencies of the input clock signal over which a particular DLL circuit can operate is typically limited. The primary factors which typically limit the operating frequency range of a DLL are the complexity of the large transistor chains and the long lock-in periods that are required for large frequency ranges. The range of clocking frequencies over which a computing device such as a dynamic random access memory (DRAM), can operate is often limited by the operating frequency range of the DLL of the DRAM.